FAPEC in an FPGA: a simple low-power solution for data compression in space

Alberto G. Villafranca; Shan Mignot; Jordi Portell; Enrique García-Berro

doi:10.1117/12.895138

16 September 2011 FAPEC in an FPGA: a simple low-power solution for data compression in space

Alberto G. Villafranca, Shan Mignot, Jordi Portell, Enrique García-Berro

Proceedings Volume 8157, Satellite Data Compression, Communications, and Processing VII; 81570I (2011) https://doi.org/10.1117/12.895138
Event: SPIE Optical Engineering + Applications, 2011, San Diego, California, United States

Abstract

Future space missions are based on a new generation of instruments. These missions find a serious constraint in the telemetry system, which cannot download to ground the large volume of data generated. Hence, data compression algorithms are often mandatory in space, despite the modest processing power usually available on-board. We present here a compact solution implemented in hardware for such missions. FAPEC is a lossless compressor which typically can outperform the CCSDS 121.0 recommendation on realistic data sets. With efficiencies higher than 90% of the Shannon limit in most cases - even in presence of noise or outliers - FAPEC has been successfully validated in its software version as a robust low-complexity alternative to the recommendation. This work describes the FAPEC implementation on an FPGA, targeting the space-qualified Actel RTAX family. We prove that FAPEC is hardwarefriendly and that it does not require external memory. We also assess the correct operation of the prototype for an initial throughput of 32 Mbits/s with very low power consumption (about 20 mW). Finally, we discuss further potential applications of FAPEC, and we set the basis for the improvements that will boost FAPEC performance beyond the 100 Mbit/s level.

Citation Download Citation

Alberto G. Villafranca, Shan Mignot, Jordi Portell, and Enrique García-Berro "FAPEC in an FPGA: a simple low-power solution for data compression in space", Proc. SPIE 8157, Satellite Data Compression, Communications, and Processing VII, 81570I (16 September 2011); https://doi.org/10.1117/12.895138

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
9 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Field programmable gate arrays

Prototyping

Data compression

Clocks

Monte Carlo methods

Calibration

Space operations

Show All Keywords

Keywords/Phrases

Search In:

Publication Years