Paper
30 October 2009 A novel parallel architecture for real-time image processing
Junhong Hu, Tianxu Zhang, Sheng Zhong, Xujun Chen
Author Affiliations +
Proceedings Volume 7497, MIPPR 2009: Medical Imaging, Parallel Processing of Images, and Optimization Techniques; 74970O (2009) https://doi.org/10.1117/12.832832
Event: Sixth International Symposium on Multispectral Image Processing and Pattern Recognition, 2009, Yichang, China
Abstract
A novel DSP/FPGA-based parallel architecture for real-time image processing is presented in this paper, DSPs are the main processing unit and FPGAs are used to be logic units for image interface protocol, image processing, image display, synchronization communication portocol of DSPs and DSP's reprogramming interface of 422/485. The presented architecture is composed of two modules: the preprocessing module and the processing module, and the latter is extendable for better performance. Modules are connected by LINK communication port, whose LVDS protocol has the ability of anti-jamming. And DSP's programs can be updated easily by 422/485 with PC's serial port. Analysis and experiments result shows that the prototype with the proposed parallel architecture has many promising charactersitics such as powerful computing capability, broad data transfer bandwidth, and is easy to be extended and updated.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Junhong Hu, Tianxu Zhang, Sheng Zhong, and Xujun Chen "A novel parallel architecture for real-time image processing", Proc. SPIE 7497, MIPPR 2009: Medical Imaging, Parallel Processing of Images, and Optimization Techniques, 74970O (30 October 2009); https://doi.org/10.1117/12.832832
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Cited by 1 scholarly publication.
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KEYWORDS
Digital signal processing

Field programmable gate arrays

Image processing

Telecommunications

Real time image processing

Transceivers

Computer architecture

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