Paper
1 April 2009 Important challenges for line-width-roughness reduction
Hidetami Yaegashi, M. Kushibiki, E. Nishimura, S. Shimura, F. Iwao, T. Kawasaki, K. Hasebe, H. Murakami, A. Hara, K. Yabe
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Abstract
It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary, is measured in each process step of spacer process.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hidetami Yaegashi, M. Kushibiki, E. Nishimura, S. Shimura, F. Iwao, T. Kawasaki, K. Hasebe, H. Murakami, A. Hara, and K. Yabe "Important challenges for line-width-roughness reduction", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72732H (1 April 2009); https://doi.org/10.1117/12.814126
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CITATIONS
Cited by 3 scholarly publications.
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KEYWORDS
Line width roughness

Etching

Double patterning technology

Silica

Photomasks

Scanners

Chemical vapor deposition

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