Paper
4 April 2008 Process-induced bias: a study of resist design and process implications
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Abstract
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer variations, compensation by exposure dose and/or PEB temperature, have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In a previous study, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, both metrics demonstrated that using PEB temperature to control across wafer CD variation was preferable to using dose compensation. The previous study was limited to a single resist and variations to track and scanner processing were kept to a minimum. Further examination of additional resist materials has indicated that significant variation in dose and PEB temperature induced CD biases exist from material to material. It is the goal of this work to understand how resist design, as well as track and scanner processing, impact process induced bias (PIB). This is accomplished by analyzing full resist models for a range of resists that exhibit different dose and PEB temperature PIB behavior. From these models, the primary resist design contributors to PIB are isolated. A sensitivity analysis of the primary resist design as well as track and scanner processing effects will also be simulated and presented.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Carlos Fonseca, Steven Scheer, Michael Carcasi, Tsuyoshi Shibata, and Takahisa Otsuka "Process-induced bias: a study of resist design and process implications", Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 692327 (4 April 2008); https://doi.org/10.1117/12.773187
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KEYWORDS
Diffusion

Semiconducting wafers

Critical dimension metrology

Photoresist processing

Temperature metrology

Calibration

Scanners

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