High throughput wafer defect monitor for integrated metrology applications in photolithography

Nagaraja Rao; Patrick Kinney; Anand Gupta

doi:10.1117/12.772384

25 March 2008 High throughput wafer defect monitor for integrated metrology applications in photolithography

Nagaraja Rao, Patrick Kinney, Anand Gupta

Proceedings Volume 6922, Metrology, Inspection, and Process Control for Microlithography XXII; 69223B (2008) https://doi.org/10.1117/12.772384
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Citation Download Citation

Nagaraja Rao, Patrick Kinney, and Anand Gupta "High throughput wafer defect monitor for integrated metrology applications in photolithography", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69223B (25 March 2008); https://doi.org/10.1117/12.772384

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