Paper
16 April 2008 Sampling for advanced overlay process control
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Abstract
Overlay metrology and control have been critical for successful advanced microlithography for many years, and are taking on an even more important role as time goes on. Due to throughput constraints it is necessary to sample only a small subset of overlay metrology marks, and typical sample plans are static over time. Standard production monitoring and control involves measuring sufficient samples to calculate up to 6 linear correctables. As design rules shrink and processing becomes more complex, however, it is necessary to consider higher order modeled terms for control, fault detection, and disposition. This in turn, requires a higher level of sampling. Due to throughput concerns, however, careful consideration is needed to establish a base-line sampling, and higher levels of sampling can be considered on an exception-basis based on automated trigger mechanisms. The goal is improved scanner control and lithographic cost of ownership. This study addresses tools for establishing baseline sampling as well as motivation and initial results for dynamic sampling for application to higher order modeling.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
DongSub Choi, Pavel Izikson, Doug Sutherland, Kara Sherman, Jim Manka, and John C. Robinson "Sampling for advanced overlay process control", Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69222U (16 April 2008); https://doi.org/10.1117/12.772738
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Overlay metrology

Semiconducting wafers

Process control

Metrology

Error analysis

Scanners

Time metrology

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