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An automated litho-aware design migration solution has been implemented to enable designers to port existing IP layouts
(custom, library, and block) to nanometer technologies while optimizing layout printability and silicon yield.
With rapidly shrinking technology nodes, the industry consolidation toward fabless or fab-lite manufacturing, demand
for second-sourcing and dramatic increase in cost of IP development, the automation of "vertical" (between nodes) and
'horizontal" (between chip manufacturers) migration becomes a very important task. The challenge comes from the fact
that even within the same technology node design and process-induced rules deviate substantially among different IDMs
and foundries, which leads to costly, error-prone and time consuming design modifications. At the same time, fast and
reliable adjustments to design and ability to switch between processes and chip manufacturers could represent significant
improvement to TTM, and respectively improving ROI. Using conservative rules (or restricted design rules) is not
always a viable option because of the area, performance and yield penalties. The difficulty of migration is augmented by
the fact that design rules are not sufficient to guaranty good printability, maximum process window and high yield.
Model-based detection of lithography-induced systematic yield-limiting defects (a.k.a. hotspots) is becoming a vital part
of the design-for-manufacturing flow for advanced technology nodes at 65nm and below. Driven by customer demand, a
collaborative effort between EDA vendors provides a complete design-for-manufacturing migration solution that allows
sub-65 nanometer designers to comprehensively address the impact of manufacturing variations on design yield and
performance during layout migration. First, the physical hard IP is migrated from its existing 90nm process to a more
advanced 65 and 45 nm processes, resulting in an area-optimized DRC-clean 65nm design retaining the original
hierarchy to facilitate further editing and design verification the original hierarchy is maintained. Then, the design
manufacturability is checked using a model-based hotspot detection solution, applying foundry-certified models. Along
with hotspots, it is also critical for the hotspot detection tool to generate directives on how to modify the layout to fix
hotspots and prevent creation of new hotspots. Several alternative fixing guidelines, ranked by amount of design
perturbation, are generated to provide focus and maximum flexibility to the correction tool. The correction tool reads
hotspot locations, severities along with the fixing guidelines, identifies area to be fixed and converts the fixing guidelines
into geometry constraints. Correction is then done on each area while respecting design rules, managing ripple effects
through multiple layers and maintaining the hierarchy. When all the corrections are completed areas that have been
affected are identified to allow these to be incrementally checked by the lithography verification tool (LPC) and re-assembled.
In case new or residual hotspots are detected, this fix-verify flow iterates over to converge on a DRC and
lithography-compliant design. Usually no more than three iterations are needed to output hotspot-free, DRC and Lithocompliant
design. We present the results of this fully automated lithography-aware migration flow on layout IPs ranging
from 65 nm to 45 nm design and migrated across foundries. Results show substantial layout quality improvements,
reduced design sensitivity to process variability by eliminating hotspots. Run-time and hotspot fixing performance are
shown.
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