Circuit size optimization with multiple sources of variation and position dependant correlation

Qian Ying Tang; Paul Friedberg; George Cheng; Costas J. Spanos

doi:10.1117/12.711794

21 March 2007 Circuit size optimization with multiple sources of variation and position dependant correlation

Qian Ying Tang, Paul Friedberg, George Cheng, Costas J. Spanos

Author Affiliations +

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65210P (2007) https://doi.org/10.1117/12.711794
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

The growing impact of process variation on circuit performance requires statistical design approaches in which circuits are designed and optimized subject to an estimated variation. Previous work [1] has shown that by including extra margins in each of the gate delays and optimizing the gate sizes, the circuit delay variation can be reduced by half. Our work goes further by deploying extended models that include delay variations due to V_th and L_eff, as well as position dependant variation. Two types of models have been proposed to account for various variations: 1) a model that explicitly adds spatial correlation terms to the design objective; 2) a model that implicitly includes such effect through the use of a modified version of Pelgrom's model. These design models are used to size a 32-bit Ladner-Fischer adder and the circuit delay distributions are obtained from Monte Carlo simulations. The analysis shows that both types of models have a noticeable performance improvements over the model presented in [1]. In addition, the second model appears to be a more adequate method for modeling various variation components and has a better performance over the first model; the drawback is a more complicated object function.

Citation Download Citation

Qian Ying Tang, Paul Friedberg, George Cheng, and Costas J. Spanos "Circuit size optimization with multiple sources of variation and position dependant correlation", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210P (21 March 2007); https://doi.org/10.1117/12.711794

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

;

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE