Prediction of interconnect delay variations using pattern matching

Eric Y. Chin; Juliet A. Holwill; Andrew R. Neureuther

doi:10.1117/12.712257

21 March 2007 Prediction of interconnect delay variations using pattern matching

Eric Y. Chin, Juliet A. Holwill, Andrew R. Neureuther

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65210I (2007) https://doi.org/10.1117/12.712257
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

An exploratory Process Variation Net Scanning (PVNS) approach to estimate interconnect delay variations is presented. It is shown that the geometrical response of lithographic nonidealities can be quickly predicted to first order with Pattern Matching. This concept can be extended to other process nonidealities by developing Maximum Lateral Impact Functions to capture the effects of variations in conductor sidewall angle and thickness from etch and CMP processes. The geometrical response for each variation can then be used to model the effective change in resistance and capacitance and perturb the corresponding values in the extracted netlist. The impact of PVNS is demonstrated using a 90nm digital design, and the runtime analysis indicates that this approach may potentially be twice as fast as traditional extraction. This allows for fast electrical analysis of independent process variations on different interconnect layers instead of traditional best and worst case corner analyses.

Citation Download Citation

Eric Y. Chin, Juliet A. Holwill, and Andrew R. Neureuther "Prediction of interconnect delay variations using pattern matching", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210I (21 March 2007); https://doi.org/10.1117/12.712257

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