Estimating adders for a low density parity check decoder

Braden J. Phillips; Daniel R. Kelly; Brian W. Ng

doi:10.1117/12.680199

25 August 2006 Estimating adders for a low density parity check decoder

Braden J. Phillips, Daniel R. Kelly, Brian W. Ng

Proceedings Volume 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI; 631302 (2006) https://doi.org/10.1117/12.680199
Event: SPIE Optics + Photonics, 2006, San Diego, California, United States

Abstract

Low density parity check decoders use computation nodes with multioperand adders on their critical path. This paper describes the design of estimating multioperand adders to reduce the latency, power and area of these nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it is found that the estimating adders do not degrade the frame error rate.

Citation Download Citation

Braden J. Phillips, Daniel R. Kelly, and Brian W. Ng "Estimating adders for a low density parity check decoder", Proc. SPIE 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, 631302 (25 August 2006); https://doi.org/10.1117/12.680199

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