Design-friendly DFM rule

Morimi Osawa; Takayoshi Minami; Hiroki Futatsuya; Satoru Asai

doi:10.1117/12.656271

13 March 2006 Design-friendly DFM rule

Morimi Osawa, Takayoshi Minami, Hiroki Futatsuya, Satoru Asai

Proceedings Volume 6156, Design and Process Integration for Microelectronic Manufacturing IV; 61560G (2006) https://doi.org/10.1117/12.656271
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

We proposed a design-friendly DFM rule intended to improve circuit performance. To reduce variations in the gate length, we applied active usage of preferred gate spaces and optimized the lithographic conditions. We selected the spaces to take into account the layouts that are used most frequently in actual design, so that many designers who are worrying about chip area and performance can follow the rule. The effect of our method was evaluated for 65-nm node technology. From the viewpoint of gate length, parallel usage of design following the rule and optimization lead to an 8% decrease in variation, and a 38% decrease in the mean difference from the targeted gate length. We also evaluated the effect on delays using an accurate method that can treat both statistical and systematic variation. The difference in the average delay from the targeted value was reduced from about 1% to less than 0.1%, and a 10% improvement in delay variation was observed.

Citation Download Citation

Morimi Osawa, Takayoshi Minami, Hiroki Futatsuya, and Satoru Asai "Design-friendly DFM rule", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560G (13 March 2006); https://doi.org/10.1117/12.656271

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