A high productivity low defectivity develop process for 193nm lithography

George Mack; Steven Consiglio; Jeffrey Bright; Kenichi Ueda; Tom Winter

doi:10.1117/12.656664

29 March 2006 A high productivity low defectivity develop process for 193nm lithography

George Mack, Steven Consiglio, Jeffrey Bright, Kenichi Ueda, Tom Winter

Proceedings Volume 6153, Advances in Resist Technology and Processing XXIII; 61530T (2006) https://doi.org/10.1117/12.656664
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

Minimizing defectivity, improving critical dimension control and improving productivity continue to be key drivers for 300mm IC manufacturing. New and unique hardware and process solutions are required to meet both technology and production demands. IBM is evaluating a new and unique resist developer hardware process. The key elements of the new process are 1) the impact or contact of the developer is uniform on the resist surface. 2) defects due to slow dissolution and redeposition are reduced, 3) developer consumption is reduced up to 60% and 4) the process time is up to 40% shorter than common develop processes. This paper presents results of our evaluation of the new developer hardware and process, and demonstrates that this is a robust process exhibiting good CD control with low defectivity and high throughput.

Citation Download Citation

George Mack, Steven Consiglio, Jeffrey Bright, Kenichi Ueda, and Tom Winter "A high productivity low defectivity develop process for 193nm lithography", Proc. SPIE 6153, Advances in Resist Technology and Processing XXIII, 61530T (29 March 2006); https://doi.org/10.1117/12.656664

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