Transient SPICE model for trap related current lag in devices

Saif Uz Zaman; Anthony Edward Parker

doi:10.1117/12.637951

5 January 2006 Transient SPICE model for trap related current lag in devices

Proceedings Volume 6035, Microelectronics: Design, Technology, and Packaging II; 60351L (2006) https://doi.org/10.1117/12.637951
Event: Microelectronics, MEMS, and Nanotechnology, 2005, Brisbane, Australia

Abstract

Traps at the surface of devices cause gate lag, which is the delayed response of drain current to a step change of gate voltage. The effect of gate lag limits the performance of devices and integrated circuits such as digital circuits, digital radio systems. The manifestation of gate lag in the frequency domain is transconductance and drain conductance dispersion. Gate lag is usually caused by surface hole trapping. Traps at the surface are charged negatively during turn-off of the devices. The negative charge turns the device further off. After turnon, these negative charges decay by means of capturing holes, which turns the device further on. The finite time related to trap charging and discharging results in gate lag. Pulsed measurements have been carried out to observe and measure this current lag in HEMT devices. Drain voltage has been found to have significant effect on the time constant of carrier trapping. Prior knowledge of the lag enables one to modify the design and selecting proper bias point for a specific application. For this purpose, a SPICE model has been developed to simulate gate lag in devices. The time lag is modelled by an RC time constant. Depending on the drain voltage, this time constant changes from 10ms to 1us. The model also predicts the transient gate current for gate voltage going down towards pinch-off. The model has further been tested for near half the saturated drain current. Two-tone intermodulation simulation is being investigated with the model.

Citation Download Citation

Saif Uz Zaman and Anthony Edward Parker "Transient SPICE model for trap related current lag in devices", Proc. SPIE 6035, Microelectronics: Design, Technology, and Packaging II, 60351L (5 January 2006); https://doi.org/10.1117/12.637951

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available