Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder

Amit Kumar Gupta; Saeid Nooshabadi; Juan Montiel-Nelson

doi:10.1117/12.608585

30 June 2005 Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder

Amit Kumar Gupta, Saeid Nooshabadi, Juan Montiel-Nelson

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608585
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

In this paper we present the VLSI architecture for the buffer for tier-I of EBCOT encoder of JPEG2000. The buffer allows the integration of bit plane coder and arithmetic coder module employing concurrent symbol processing technique. The buffer architecture is optimized by exploiting the natural image statistics to optimally choose the buffer length parameter. The overall architecture is implemented using Altera FPGA and experimental results show a savings of 59% in the hardware cost with minimal reduction in the overall throughput.

Citation Download Citation

Amit Kumar Gupta, Saeid Nooshabadi, and Juan Montiel-Nelson "Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608585

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available