Paper
10 May 2005 Overlay mark performance: a simulation study
Author Affiliations +
Abstract
The overlay budgets in leading-edge processes are expected to shrink below 20nm within the next 12-24 months. The demand for ever higher accuracies of overlay metrology for the 65nm node and below drive the development and design of new optical metrology solutions. In this work, we present new results as a continuation of the work we have previously reported on an overlay metrology simulation platform, capable of simulating the entire overlay measurement process. The simulation platform is used for modeling both the optical effects of the overlay metrology tool and the target process and design related effects on the overlay metrology performance. Using this simulation platform we have modeled target proximity effects limiting target size reduction, and process variation effects on overlay performance.
© (2005) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Aviv Frommer and Joel L. Seligson "Overlay mark performance: a simulation study", Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); https://doi.org/10.1117/12.599059
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CITATIONS
Cited by 3 scholarly publications and 1 patent.
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KEYWORDS
Overlay metrology

Signal processing

Photoresist processing

Semiconducting wafers

Computer simulations

Device simulation

Optical design

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