Design of the SPI interface of 10-gigabit ethernet with FPGA

Hong Chen; Zhao Liu; Li Su; Depeng Jin; Lieguang Zeng

doi:10.1117/12.571689

8 February 2005 Design of the SPI interface of 10-gigabit ethernet with FPGA

Hong Chen, Zhao Liu, Li Su, Depeng Jin, Lieguang Zeng

Proceedings Volume 5626, Network Architectures, Management, and Applications II; (2005) https://doi.org/10.1117/12.571689
Event: Asia-Pacific Optical Communications, 2004, Beijing, China

Abstract

Due to its low cost and packet data efficiency, Ethernet has been one of the most influential technologies for Local Area Networks (LAN). Moreover, the 10-Gigabit Ethernet has begun to move Ethernet from the LAN out to encompass the metro area network. The technology features, protocol architecture and the frame format are introduced. In order to realize the logical boundary between the physical layer and the link layer, the protocol of SPI (System Packet Interface) level4 is adopted. A method of realizing the SPI interface of 10-Gigabit Ethernet is put forward and the function block diagram is presented. In order to reduce the power waste of the chip, the parallel algorithm is chosen in the design.

Citation Download Citation

Hong Chen, Zhao Liu, Li Su, Depeng Jin, and Lieguang Zeng "Design of the SPI interface of 10-gigabit ethernet with FPGA", Proc. SPIE 5626, Network Architectures, Management, and Applications II, (8 February 2005); https://doi.org/10.1117/12.571689

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