Metrology of LER: influence of line-edge roughness (LER) on transistor performance

Atsuko Yamaguchi; Katsuhiko Ichinose; Satoshi Shimamoto; Hiroshi Fukuda; Ryuta Tsuchiya; Kazuhiro Ohnishi; Hiroki Kawada; Takashi Iizumi

doi:10.1117/12.534631

24 May 2004 Metrology of LER: influence of line-edge roughness (LER) on transistor performance

Atsuko Yamaguchi, Katsuhiko Ichinose, Satoshi Shimamoto, Hiroshi Fukuda, Ryuta Tsuchiya, Kazuhiro Ohnishi, Hiroki Kawada, Takashi Iizumi

Author Affiliations +

Proceedings Volume 5375, Metrology, Inspection, and Process Control for Microlithography XVIII; (2004) https://doi.org/10.1117/12.534631
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined. First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-μm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.

Citation Download Citation

Atsuko Yamaguchi, Katsuhiko Ichinose, Satoshi Shimamoto, Hiroshi Fukuda, Ryuta Tsuchiya, Kazuhiro Ohnishi, Hiroki Kawada, and Takashi Iizumi "Metrology of LER: influence of line-edge roughness (LER) on transistor performance", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.534631

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