Code compression for VLIW embedded processors

Emiliano Piccinelli; Roberto Sannino

doi:10.1117/12.524755

19 April 2004 Code compression for VLIW embedded processors

Emiliano Piccinelli, Roberto Sannino

Proceedings Volume 5309, Embedded Processors for Multimedia and Communications; (2004) https://doi.org/10.1117/12.524755
Event: Electronic Imaging 2004, 2004, San Jose, California, United States

Abstract

The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the “SlimCode” proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

Citation Download Citation

Emiliano Piccinelli and Roberto Sannino "Code compression for VLIW embedded processors", Proc. SPIE 5309, Embedded Processors for Multimedia and Communications, (19 April 2004); https://doi.org/10.1117/12.524755

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