Performance analysis of high-accuracy CMOS sample-and-hold circuits

Hai P. Le; Aladin Zayegh; Jugdutt Singh

doi:10.1117/12.530415

30 March 2004 Performance analysis of high-accuracy CMOS sample-and-hold circuits

Hai P. Le, Aladin Zayegh, Jugdutt Singh

Proceedings Volume 5274, Microelectronics: Design, Technology, and Packaging; (2004) https://doi.org/10.1117/12.530415
Event: Microelectronics, MEMS, and Nanotechnology, 2003, Perth, Australia

Abstract

This paper presents the performance analysis of different high-accuracy sample-and-hold circuit (SHC) techniques using CMOS technology. The paper begins with a detailed analysis of the major factors that limit the accuracy of a fundamental SHC. Then different techniques to implement high-accuracy SHCs are described. SHC employing transmission gate and SHC using feedback loop with compensation capacitor, as well as the fundamental SHC, were all implemented and tested and performance results demonstrate the superiority of each SHC schemes. For comparison reasons, the three SHCs were operated at a speed of 330 MHz. Results indicate that an increase of accuracy of 95% is achieved and the maximum sampling speed is increased by 15% when the SHC using feedback loop is used instead of the fundamental SHC. These characteristics make this device better candidate for many applications where speed and accuracy are the major factors.

Citation Download Citation

Hai P. Le, Aladin Zayegh, and Jugdutt Singh "Performance analysis of high-accuracy CMOS sample-and-hold circuits", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); https://doi.org/10.1117/12.530415

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