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Control of the transistor gate critical dimension (CD) on the order of a few nanometers is a top priority in many advanced fabs like Chartered. Each nanometer deviation from the targeted gate length implicitly means that the operational speed of the devices are also affected. In transistors, for example, when the post-etch gate CD is too small, the threshold voltage shift and leakage current can render the device inoperative. Increasingly, advances in logic devices are requiring technological improvements, and fab economics are necessitating greater productivity. In an automated foundry environment, the target gate CD can be achieved in more than one way. For example, using in-line process control by linking the lithography and etch tools can improve CD performance beyond what each individual tool can achieve. In this approach, the etch process is used to compensate for incoming CD variation and reduce final wafer-to-wafer CD variation. However, this feed-forward approach of CD control involves a one-time heavy investment in integrated optical CD (OCD) metrology as well as an integrated server to feedback process control that will automatically adjust tools and process steps in high-volume, wafer-fabrication lines. The other considerations are the time involved in retrofitting and the complexity of qualifying these integrated tools after retrofit. A second way to do it is to change the sigma slightly to match tool to tool. But by so doing, process window parameters like DOF and such are also affected. This technique is adopted by many ASML users as the new ASML illumination setting (new NA/Sigma) is fairly easy to set up. However, the problem is that it makes the system unmanageable on large scale especially in a foundry environment. The work done here involves seeking a more economical approach of CD control without modifying the hardware of existing tool set to pave the path for a more demanding CD matching requirement between lithography tools. It is necessary not only to ensure the same process exposure conditions used from different tools to achieve a good CD matching for large scale manufacturing, but also to ensure the same CD matching performance for some critical pitches if not all. This is important for a foundry which runs a myraid range of products having different line pitches for different gate layers. DUV optical lithography has met the shrinking CD requirements for 0.13um technology node. The introduction of Optical Proximity Correction (OPC) on the reticle, has further prolonged the binary mask life. The procedure provided herein attempts to render tool dedication as a result of non-compatibility of OPC design rule unnecessary. In this paper, the authors will present the challenges faced in the course of matching the lithography tool set for the large scale manufacturability in terms of stepper energy and iso-dense CD bias, such that the exposure dose requested and the real dose applied on the wafer level is the same for any one process tool set and is within the tolerable range of iso-dense CD bias of 4nm.
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