GaAs wafer overlay performance affected by annealing heat treatment: I

Ying Liu; Iain Black

doi:10.1117/12.473502

16 July 2002 GaAs wafer overlay performance affected by annealing heat treatment: I

Ying Liu, Iain Black

Proceedings Volume 4689, Metrology, Inspection, and Process Control for Microlithography XVI; (2002) https://doi.org/10.1117/12.473502
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

During wafer fabrication overlay performance is affected by various factors, such as the quality and location of the alignment marks, film deposition, tool control and wafer distortion during processing, e.g. after undergoing a high temperature treatment, etc. In our study, an investigation was conducted on wafer distortion by analyzing registration data measured on IVS120 overlay CD tool. The data was then analyzed using MONO-LITH software. The Overlay Yield Map analysis using the modeled data displays or predicts field yield across the entire wafer quantified by a predefined specification limit-error limit of misalignment. This analysis provides information on overlay performance of the process. The experimental results indicate that the wafer orientation before the loading in the RTA chamber plays an important role in the overlay performance, causing significant variation in overlay performance. The overall error could be as large as 0.25 micrometers though wafer orientation in the chamber could improve this, however different oven chambers were found to give different preferred orientation.

Citation Download Citation

Ying Liu and Iain Black "GaAs wafer overlay performance affected by annealing heat treatment: I", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473502

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KEYWORDS

Semiconducting wafers

Overlay metrology

Distortion

Gallium arsenide

Annealing

Error analysis

Image registration

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