Submicron high-aspect-ratio silicon beam etch

Gary O'Brien; David J. Monk; Khalil Najafi

doi:10.1117/12.448983

21 November 2001 Submicron high-aspect-ratio silicon beam etch

Gary O'Brien, David J. Monk, Khalil Najafi

Proceedings Volume 4592, Device and Process Technologies for MEMS and Microelectronics II; (2001) https://doi.org/10.1117/12.448983
Event: International Symposium on Microelectronics and MEMS, 2001, Adelaide, Australia

Abstract

High aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool. Process input parameters are varied using high/low values for etch cycle time, passivation cycle time, RF power, and SF₆ flow rate. The silicon etch process is characterized using photo-resist masked trench arrays varied from 1.5micrometers through 6micrometers in both width and spacing. A design of experiments (DOE) approach is used to model the following measured outputs: 1) trench depth (R²=0.985), 2) lateral trench etch (R²=0.852), 3) trench sidewall angle (R²=0.815), and 4) aspect ratio dependent etch (R²=0.942), where R² represents the correlation between actual and model predicted values. The presented characterization models are employed to form beams as small as 300nm wide beams etched to a depth >15micrometers with near vertical sidewalls using standard photolithography equipment. In addition, the provided models are exploited to produce a dual re-entrant/tapered beam etch release process. Released silicon beams are demonstrated over 1200micrometers long and 30micrometers thick with a base width of 300nm.

Citation Download Citation

Gary O'Brien, David J. Monk, and Khalil Najafi "Submicron high-aspect-ratio silicon beam etch", Proc. SPIE 4592, Device and Process Technologies for MEMS and Microelectronics II, (21 November 2001); https://doi.org/10.1117/12.448983

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