Low-cost wafer level packaging process

Rahul Kapoor; Swee Yong Khim; Goh Hin Hwa

doi:10.1117/12.404877

23 October 2000 Low-cost wafer level packaging process

Rahul Kapoor, Swee Yong Khim, Goh Hin Hwa

Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404877
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

Today, semiconductors are being connected to other components of the system through three main interconnect technologies - Wirebond, TAB and Solder bump. Of the three technologies, use of solder bump provides the lowest impedance electrical path and a high er I/O density as compared to wirebond and TAB. Wafer bumping is often accompanied by a need for redistribution of the current carrying pads on the silicon in order to reduce the substrate cost and better manufacturing yields, Besides, there is a need to deposit a metallic layer underneath the bump for good reliability of the packaged system. The two widely used processes used for depositing a thin metal film, either for redistribution or UBM are Physical Vapor Deposition and evaporation. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for going towards wafers level packaging solutions in order to minimize the packaging cost and giving high production rates.

Citation Download Citation

Rahul Kapoor, Swee Yong Khim, and Goh Hin Hwa "Low-cost wafer level packaging process", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404877

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