Paper
27 August 1999 Frequency distribution modeling for high-speed microprocessors using on-chip ring oscillators
John M. Carulli Jr., Derek C. Wrobbel, Aswin Mehta, Kenneth E. Krause Jr., Brad E. Campbell, Fred A. Valente
Author Affiliations +
Abstract
It is critical for success in the microprocessor business to understand the relationship between yield and speed- performance. This paper outlines a method for modeling device speed distribution and yield using on-chip ring-oscillator measurements. The modeling method is used in production on the UltraSPARCTM-II family of microprocessors. Lot-level speed distributions are predicted within 10% by speed-bin and quarterly distributions within 5% by speed-bin. Graphs are generated to show the relationship between business and process concerns.
© (1999) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
John M. Carulli Jr., Derek C. Wrobbel, Aswin Mehta, Kenneth E. Krause Jr., Brad E. Campbell, and Fred A. Valente "Frequency distribution modeling for high-speed microprocessors using on-chip ring oscillators", Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); https://doi.org/10.1117/12.361341
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Cited by 1 scholarly publication.
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KEYWORDS
Manufacturing

Data modeling

Critical dimension metrology

Instrument modeling

Semiconducting wafers

Silicon

Design for manufacturability

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