Queueing model for an ATM multiplexer with unequal input/output link capacities

Y. H. Long; T. K. Ho; A. B. Rad; S. P. S. Lam

doi:10.1117/12.325889

7 October 1998 Queueing model for an ATM multiplexer with unequal input/output link capacities

Y. H. Long, T. K. Ho, A. B. Rad, S. P. S. Lam

Proceedings Volume 3530, Performance and Control of Network Systems II; (1998) https://doi.org/10.1117/12.325889
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States

Abstract

We present a queuing model for an ATM multiplexer with unequal input/output link capacities in this paper. This model can be used to analyze the buffer behaviors of an ATM multiplexer which multiplexes low speed input links into a high speed output link. For this queuing mode, we assume that the input and output slot times are not equal, this is quite different from most analysis of discrete-time queues for ATM multiplexer/switch. In the queuing analysis, we adopt a correlated arrival process represented by the Discrete-time Batch Markovian Arrival Process. The analysis is based upon M/G/1 type queue technique which enables easy numerical computation. Queue length distributions observed at different epochs and queue length distribution seen by an arbitrary arrival cell when it enters the buffer are given.

Citation Download Citation

Y. H. Long, T. K. Ho, A. B. Rad, and S. P. S. Lam "Queueing model for an ATM multiplexer with unequal input/output link capacities", Proc. SPIE 3530, Performance and Control of Network Systems II, (7 October 1998); https://doi.org/10.1117/12.325889

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