Architecture of a reconfigurable system based on an embedded FPPA

Christophe Amerijckx; Jean-Didier Legat

doi:10.1117/12.327027

8 October 1998 Architecture of a reconfigurable system based on an embedded FPPA

Christophe Amerijckx, Jean-Didier Legat

Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327027
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States

Abstract

In this paper, we introduce the architecture of a new embedded field programmable processor array (E-FPPA) which consists of a low-power multiprocessor system embedded with standard programmable logic blocks and memory. Each block (processor, programmable logic,...) is coupled to a transfer controller responsible of all the transfers between blocks. Instead of using a classical crossbar interconnection network, we propose a low cost hierarchical ring which combines simple interface and high performance communications when data locally is observed. This architecture is fully scalable and is based on a numa (non- uniform access time memory) multiprocessor scheme. The core of the architecture is a small RISC processor (actually, a very low power CoolRisc has been chosen) which is embedded with programmable logic blocks (similar to standard CPLD or FPGA), static RAMs and other devices (DSP coprocessor, peripherals, ...). By using the 8-bit CoolRisc processor, an E-FPPA including a cluster of 16 processors, 16 TC, 4 Kbytes data memory and 5.5 Kbytes program memory for each processor can deliver up to 3200 Mops at 100 MHz. The chip size has been evaluated in 0.35 micrometers to 52 mm².

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Christophe Amerijckx and Jean-Didier Legat "Architecture of a reconfigurable system based on an embedded FPPA", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); https://doi.org/10.1117/12.327027

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