Improved post-etch cleaning of dual-damascene system for 0.18-um technology

Didier Louis; Catherine Peyne; Emile Lajoinie; B. Vallesi; David J. Maloney; Shihying Lee

doi:10.1117/12.324024

4 September 1998 Improved post-etch cleaning of dual-damascene system for 0.18-μm technology

Didier Louis, Catherine Peyne, Emile Lajoinie, B. Vallesi, David J. Maloney, Shihying Lee

Proceedings Volume 3508, Multilevel Interconnect Technology II; (1998) https://doi.org/10.1117/12.324024
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

A key challenge for 0.18 micrometer technology is the interconnect RC delay time, which becomes the limiting factor for device performance. This delay can be reduced by combining the use of a material of low dielectric constant between metal lines and the use of copper, which is a better conductor than aluminum. In this paper some of the difficulties of integrating these types of interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.

Citation Download Citation

Didier Louis, Catherine Peyne, Emile Lajoinie, B. Vallesi, David J. Maloney, and Shihying Lee "Improved post-etch cleaning of dual-damascene system for 0.18-μm technology", Proc. SPIE 3508, Multilevel Interconnect Technology II, (4 September 1998); https://doi.org/10.1117/12.324024

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available