Paper
28 December 1982 High Speed Charge-Coupled Device (CCD) Two-Dimensional Correlator
B. E. Burke, A. M. Chiang, W. H. McGonagle, G. R. McCully, J. F. Melia
Author Affiliations +
Proceedings Volume 0341, Real-Time Signal Processing V; (1982) https://doi.org/10.1117/12.933709
Event: 1982 Technical Symposium East, 1982, Arlington, United States
Abstract
A CCD-based two-dimensional correlator system is described which correlates a 256 x 256 image with a 32 x 32 reference in less than 1 second. The high computation rate (more than 100 million operations per second) is achieved using two high speed CCDs: a 32-stage programmable transversal filter (PTF) which correlates an analog signal with a set of 32 6-bit tap weights at a 5 MHz rate, and an accumulating memory which sums successive correlation records from the PTF. This system uses a technique which performs a series of one-dimensional correlations in the PTF and sums them in the accumulator to form the two-dimensional correlation. This approach is capable of considerable flexibility and can be extended to correlations of much larger image and reference sizes even with a transversal filter of limited length, and also to correlations of data of more than two dimensions.
© (1982) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
B. E. Burke, A. M. Chiang, W. H. McGonagle, G. R. McCully, and J. F. Melia "High Speed Charge-Coupled Device (CCD) Two-Dimensional Correlator", Proc. SPIE 0341, Real-Time Signal Processing V, (28 December 1982); https://doi.org/10.1117/12.933709
Lens.org Logo
CITATIONS
Cited by 1 scholarly publication.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Charge-coupled devices

Phase transfer function

Optical correlators

Signal processing

Clocks

Digital filtering

Logic

RELATED CONTENT

Adaptive Acoustooptic Processor
Proceedings of SPIE (January 21 1985)
Performance of the European logarithmic microprocessor
Proceedings of SPIE (December 24 2003)
New systolic array architecture for vector median filters
Proceedings of SPIE (December 28 1998)

Back to Top