Yield-enhanced routing for high-performance VLSI designs

Arunshankar Venkataraman; Howard H. Chen; Israel Koren

doi:10.1117/12.284707

11 September 1997 Yield-enhanced routing for high-performance VLSI designs

Arunshankar Venkataraman, Howard H. Chen, Israel Koren

Proceedings Volume 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III; (1997) https://doi.org/10.1117/12.284707
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

It is widely recognized that interconnects will be the main bottleneck in enhancing the performance of future deep sub-micron VLSI designs. Interconnects do not "scale" well with decreasing feature sizes and therefore dominate the delays in the integrated circuit. In addition to RC delays, crosstalk noise also contributes significantly to the delays experienced by a signal. Interconnects are more susceptible to manufacturing defects and therefore affect the product yields significantly. Recently, several channel-routing based solutions have been proposed to minimize crosstalk noise and also enhance yield of the routing. While these approaches are effective, they do not provide maximum benefits as they are either constrained by a particular design methodology or are post-routing steps which have limited scope for significant improvement. Also, design for manufacturabiity objectives have not been fully exploited by VLSI CAD tools as they do not integrate seamlessly into the conventional design flow and the added overheads make it less attractive. In this paper, we propose a modified routing algorithm that maximizes yield and reduces crosstalk noise while using minimal area for the routing. The yield enhancement objective has been integrated into the routing phase as a preferred constraint (a constraint that will be satisfied only if the primary constraints of minimal area and wire length have been satisfied) and fits well into the conventional design flow. This enables the router to produce an output which provides maximum achievable critical area reduction for the given routing solution. Post-routing layout modification is also done with the objective of minimizing the interaction area between the interconnects by exploiting the gridless property of the router. The above algorithm is incorporated into GLITTER (the gridless, variable width channel router), and the results on channel-routing benchmarks are presented. These results show a significant reduction in the critical area achievable by using the proposed algorithm.

Citation Download Citation

Arunshankar Venkataraman, Howard H. Chen, and Israel Koren "Yield-enhanced routing for high-performance VLSI designs", Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997); https://doi.org/10.1117/12.284707

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