Technology mapping for hot-carrier reliability enhancement

Zhan Chen; Israel Koren

doi:10.1117/12.284706

11 September 1997 Technology mapping for hot-carrier reliability enhancement

Zhan Chen, Israel Koren

Proceedings Volume 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III; (1997) https://doi.org/10.1117/12.284706
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

As semiconductor devices enter the deep sub-micron era, reliability has become a major issue and challenge in VLSI design. Among all the failure mechanisms, hot-carrier effect is one of those which have the most significant impact on the long-term reliability of high-density VLSI circuits. In this paper, we address the problem of minimizing hot-carrier effect during the technology mapping stage of VLSI logic synthesis. We first present a logic-level hot-carrier model, and then, based on this model, we propose a technology mapping algorithm for hot-carrier effect minimization. The proposed algorithm has been implemented in the framework of the Berkeley logic optimization package SIS. Our results show that an average of 29. 1% decrease in hot-carrier effect can be achieved by carefully choosing logic gates from cell libraries to implement given logic functions for a set of benchmarks. It has also been observed that the best design for hot-carrier effect minimization does not necessarily coincide with the best design for low power, which has long been considered as a rough measure for VLSI reliability.

Citation Download Citation

Zhan Chen and Israel Koren "Technology mapping for hot-carrier reliability enhancement", Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997); https://doi.org/10.1117/12.284706

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