Reconfigurable hardware accelerator for embedded DSP

Keith Reeves; Ken Sienski; Calvin Field

doi:10.1117/12.255831

21 October 1996 Reconfigurable hardware accelerator for embedded DSP

Keith Reeves, Ken Sienski, Calvin Field

Proceedings Volume 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic; (1996) https://doi.org/10.1117/12.255831
Event: Photonics East '96, 1996, Boston, MA, United States

Abstract

Many DSP applications require dedicated hardware to achieve acceptable levels of performance. This is particularly true of real-time applications that have strict timeline requirements on processing throughput and latency. This paper outlines an FPGA-based reconfigurable processor architecture targeted to embedded DSP applications. The processor core consists of a high gate count FPGA multichip module (MCM) supplemented with four dedicated floating point multipliers. A dual port data memory provides a 480 Mbyte/sec channel to the processor and a 240 Mbyte/sec channel to the external interface. Coefficient memories are also included for static look-up table storage. A configuration bit stream loaded from non-volatile memory or an external source is used to program the FPGA.

Citation Download Citation

Keith Reeves, Ken Sienski, and Calvin Field "Reconfigurable hardware accelerator for embedded DSP", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255831

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