Parallel processor for motion estimation

Emmanuel J.-M. Hanssens; Jean-Didier Legat

doi:10.1117/12.233317

27 February 1996 Parallel processor for motion estimation

Emmanuel J.-M. Hanssens, Jean-Didier Legat

Proceedings Volume 2727, Visual Communications and Image Processing '96; (1996) https://doi.org/10.1117/12.233317
Event: Visual Communications and Image Processing '96, 1996, Orlando, FL, United States

Abstract

A parallel processor for real-time motion estimation algorithms has been developed. It consists of several clusters of basic processing elements connected to a transfer controller that is attached to an external RAM. The architecture is parallel, allowing each cluster to work on non-overlapping image segments. It is also associative, in that the execution of a global instruction step by a processing element depends on some local conditions: moreover, lateral communications between clusters are provided, these two last features being essential for motion vector field regularization processes. Feasibility of the architecture has been evaluated with an advanced block-matching based option estimation algorithm: the ABMA. Running at a clock rate of 50 MHz, a group of 12 processing elements can real-time execute the ABMA on a common input format (CIF) image (288 by 352 pixels, at 10 Hz). A custom VLSI test circuit, consisting of one processing element and one transfer controller, has been designed in a 1 micrometer technology; the total silicon area of the test circuit is 41 mm².

Citation Download Citation

Emmanuel J.-M. Hanssens and Jean-Didier Legat "Parallel processor for motion estimation", Proc. SPIE 2727, Visual Communications and Image Processing '96, (27 February 1996); https://doi.org/10.1117/12.233317

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