Wafer flatness modeling for scanning steppers

Randal K. Goodall; Howard R. Huff

doi:10.1117/12.240143

21 May 1996 Wafer flatness modeling for scanning steppers

Randal K. Goodall, Howard R. Huff

Proceedings Volume 2725, Metrology, Inspection, and Process Control for Microlithography X; (1996) https://doi.org/10.1117/12.240143
Event: SPIE's 1996 International Symposium on Microlithography, 1996, Santa Clara, CA, United States

Abstract

Model-based analysis is used to explain previous observations regarding the distributional form and numeric relationships of several key lithographic flatness quality metrics for silicon wafers. The dominant relationships are controlled by longer wavelength (tens of millimeters) surface topography, while the distribution shapes are controlled by shorter wavelength (few millimeters) topography. A lithographic flatness modeling framework is introduced which can provide guidance for specification of silicon wafer flatness for ULSI IC products. New site flatness models show that, compared to a full-field stepper, a scanning stepper can effect improved flatness performance from wafers of similar quality.

Citation Download Citation

Randal K. Goodall and Howard R. Huff "Wafer flatness modeling for scanning steppers", Proc. SPIE 2725, Metrology, Inspection, and Process Control for Microlithography X, (21 May 1996); https://doi.org/10.1117/12.240143

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