Performance optimization of three-dimensional optoelectronic interconnection for intra-multi-chip-module clock signal distribution

Chunhe Zhao; Ray T. Chen

doi:10.1117/12.221198

18 September 1995 Performance optimization of three-dimensional optoelectronic interconnection for intra-multi-chip-module clock signal distribution

Chunhe Zhao, Ray T. Chen

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Proceedings Volume 2638, Optical Characterization Techniques for High-Performance Microelectronic Device Manufacturing II; (1995) https://doi.org/10.1117/12.221198
Event: Microelectronic Manufacturing '95, 1995, Austin, TX, United States

Abstract

The structure, fabrication, and theory of a 3D planarized optoelectronic clock signal distribution device, based on a thin light-guiding substrate in conjunction with a 2D polymer holographic grating array, are described. We have previously demonstrated a 25 GHz 1-to-42 (6 X 7) highly parallel fanout interconnect with a signal to noise ration of 10 dB¹. In this paper, theoretical work focused on generating a globally uniform fanout distribution is presented. An objective function aimed at equalizing the intensities among the fanout beams is established and optimization results are reported. Finally, the angular misalignment and wavelength dispersion problem are further discussed, together with their tolerance requirements on the size of the photoreceivers and the bandwidth of the vertical cavity surface emitting lasers integrated on the multi-chip-modules.

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Chunhe Zhao and Ray T. Chen "Performance optimization of three-dimensional optoelectronic interconnection for intra-multi-chip-module clock signal distribution", Proc. SPIE 2638, Optical Characterization Techniques for High-Performance Microelectronic Device Manufacturing II, (18 September 1995); https://doi.org/10.1117/12.221198

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KEYWORDS

Diffraction gratings

Clocks

Holography

Diffraction

Optoelectronics

Vertical cavity surface emitting lasers

Holograms

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