Paper
22 September 1995 Process design for manufacturability of GaAs MESFET integrated circuit using statistical experimental design techniques
Jian S. Wang, C. C. Teng, J. R. Middleton, Peter J. Apostolakis, Milton Feng
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Abstract
A manufacturable, directly ion implanted 0.6 micrometers GaAs metal- semiconductor field-effect transistors (MESFET) and metal-semiconductor- metal (MSM) based opto-electronic integrated circuit (OEIC) process has been developed and optimized for low cost optical data link applications. Key steps in the OEIC process have been identified and statistically quantifiable process modules have been obtained to optimize the circuit performance and achieve high process yield. The statistically significant transfer characteristics of each process module was obtained through design of experiment (DOE) and response surface modeling (RSM), by utilizing both experimental data and data from experimentally calibrated process simulators. This paper discusses the PECVD Si2N4 process module optimization and the backgating effects in GaAs ICs.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jian S. Wang, C. C. Teng, J. R. Middleton, Peter J. Apostolakis, and Milton Feng "Process design for manufacturability of GaAs MESFET integrated circuit using statistical experimental design techniques", Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); https://doi.org/10.1117/12.221451
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KEYWORDS
Field effect transistors

Gallium arsenide

Plasma enhanced chemical vapor deposition

Refractive index

Photonic integrated circuits

Data modeling

Integrated circuits

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