|
This paper reports on the results of the optimization of a high throughput sputter etch process prior to interconnect deposition with no device damage, performed on the Endura HP PVD system. The second level metallization for a 2-level metal interconnect scheme requires a pre- metallization sputter etch of the vias in order to remove the native oxide and the fluoro-carbon residues left after the ILD oxide etch. For high throughput processing, high etch rates are required along with the essential prerequisites of plasma processing, namely, good process uniformity and no electrical device damage. A high density dual-frequency system with independent control of plasma and bias powers was used to optimize the pre-metallization etch using the second level of a 256 K SRAM device test structure fabricated in a 150 mm wafer production line. Response surface methodology (RSM) was used to explore the parameter space of the sputter etch process. The rf plasma power, rf bias power and the SiO2 thickness etched were chosen as the 3 independent variables. The SiO2 etch rate, SiO2 etch uniformity, via resistance & uniformity and threshold voltage & uniformity were measured and modeled as the response variables. SiO2 etch rates from 214 A/min to 926 A/min, SiO2 etch uniformities from 1.88 to 7.27% 1-sigma, via resistances from 0.32 to 0.42 Ohms, and threshold voltages from 0.74 V were obtained. A suitably wide process window was established with the excellent process/device results and a 40% reduction in process time.
|
