Economical silicon-on-glass interconnection

Phil P. Marcoux

doi:10.1117/12.172131

1 April 1994 Economical silicon-on-glass interconnection

Phil P. Marcoux

Proceedings Volume 2174, Advanced Flat Panel Display Technologies; (1994) https://doi.org/10.1117/12.172131
Event: IS&T/SPIE 1994 International Symposium on Electronic Imaging: Science and Technology, 1994, San Jose, CA, United States

Abstract

An economical silicon on glass interconnection technique has been developed. A specially packaged semiconductor is clamped directly to the interconnecting traces deposited on the glass of a glass display. The clamping mechanism is a mechanical clamp configured so that the force is applied uniformly around the perimeter of the integrated circuit. The packaging process involves the encapsulation of the semiconductor circuits using photoforming techniques. The photoforming process known as Micro SMT encapsulates the circuit so it is sufficiently ruggedized to withstand the force of the clamp without damaging the circuit. In its ruggedized state the circuit can be handled, tested, and interconnected. The process uses masking, etching, and metalization processes common to the existing semiconductor industry. This process has been used economically and reliably over the past size years for microwave semiconductor devices. The photo formed package is physically as small as the bare circuit or a flip-chip. Unlike the use of bare integrated circuits or a flip-chips, the Micro SMT package has peripherally arranged leads. This offers the advantages of easier alignment of the chip to the glass footprint; inspect ability and testability of the interconnections.

Citation Download Citation

Phil P. Marcoux "Economical silicon-on-glass interconnection", Proc. SPIE 2174, Advanced Flat Panel Display Technologies, (1 April 1994); https://doi.org/10.1117/12.172131

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