Empirical models in semiconductor processing: optimization and assessment as simulators

Steve W. Lavelle; David Wood; A. J. Hydes

doi:10.1117/12.167365

15 February 1994 Empirical models in semiconductor processing: optimization and assessment as simulators

Steve W. Lavelle, David Wood, A. J. Hydes

Proceedings Volume 2091, Microelectronic Processes, Sensors, and Controls; (1994) https://doi.org/10.1117/12.167365
Event: Microelectronic Processing '93, 1993, Monterey, CA, United States

Abstract

If any empirical model of an experimental system is to be used to make predictions its success as a simulator needs to be determined. This is especially so in semiconductor manufacturing where process runs are expensive making the need for a reliable process simulation even more important. With many current model assessment techniques, for example `coefficients of determination', too much information about the model's fit is hidden by the attempt to describe the model's success in terms of a single variable value. In this paper the description is given of a computational approach together with a standard visual display technique which allows the simulation capabilities of a model to be more fully understood. The method described is applicable to all modelling algorithms and as such allows the utility of competing modelling philosophies to be assessed.

Citation Download Citation

Steve W. Lavelle, David Wood, and A. J. Hydes "Empirical models in semiconductor processing: optimization and assessment as simulators", Proc. SPIE 2091, Microelectronic Processes, Sensors, and Controls, (15 February 1994); https://doi.org/10.1117/12.167365

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