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A hybrid 640 x 480 PACE HgCdTe FPA is being developed to meet the needs of many applications including missile seekers and FLIR's. The device will offer full TV resolution with sensitivity much superior to PtSi, having over one-quarter million pixels. The hybrid is comprised of a PACE HgCdTe detector array having nominal 5 pm cut- off wavelength, mated to a high speed CMOS readout having high charge-handling capacity. The HgCdTe detectors are being fabricated on alternative sub- strates using Rockwell's mature PACE-1 and advanced PACE-3 detector growth processes. The PACE-3 process, which is currently being developed, involves the MOCVD of HgCdTe on buffered silicon sub- strates. Since a PACE-3 hybrid uses silicon substrates for both the readout and detector, excellent hybrid reliability is expected even after thousands of thermal cycles. Based on 2562 results to date, the PACE-3 detectors will have mean quantum efficiency < 30% with rms respons- ivity nonuniformity < 8% across a typical array. The mean detector RoA product measured on parallel test samples is typically greater than 104 sl-cm2 at 80K. PACE-1 detectors in this cell size have RoA < 105 o-cm2 at 80K and quantum efficiency < 60%. The 640 x 480 readout uses a CMOS switched-FET architecture with direct injection input. The device is structured in four quadrants and has four high speed outputs. The unit cell size is 27 x 27 um 2. Included in the cell is a built-in test feature allowing full readout characterization prior to hybridization. Maximum data rate of each output is < 10 MHz. The 640 x 480 thus generates over 109 bits/sec of video information. The chip was fabricated using 1.25 um lithography at a silicon foundry. Very good functional yield of the < 3 cm2 dice was achieved.
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