Systolic architecture for discrete wavelet transform

Henry Y.H. Chuang; Ching-Chung Li; HyungJun Kim

doi:10.1117/12.58395

30 April 1992 Systolic architecture for discrete wavelet transform

Henry Y.H. Chuang, Ching-Chung Li, HyungJun Kim

Proceedings Volume 1659, Image Processing and Interchange: Implementation and Systems; (1992) https://doi.org/10.1117/12.58395
Event: SPIE/IS&T 1992 Symposium on Electronic Imaging: Science and Technology, 1992, San Jose, CA, United States

Abstract

The wavelet transform provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a scanned signal into localized contributions for multiscale analysis. This paper presents a systolic architecture which can compute the discrete wavelet transform (DWT) in an efficient manner. When the number of data points windowed in the input is N equals 2m, our DWT systolic architecture is composed of m layers of identical 1-dimensional arrays, which compute the high-pass and the low-pass filtered components simultaneously. Input data string can enter and be processed 'on-the-fly' continuously at the rate of one data point per clock period T. The computation time for a large number of successive DWT problems is NT per DWT.

Citation Download Citation

Henry Y.H. Chuang, Ching-Chung Li, and HyungJun Kim "Systolic architecture for discrete wavelet transform", Proc. SPIE 1659, Image Processing and Interchange: Implementation and Systems, (30 April 1992); https://doi.org/10.1117/12.58395

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