Miniaturized low-power parallel processor for space applications

William J. Jacobi; Preben D. Jensen; Nicholas J. Teneketges; Leo A. Wadsworth

doi:10.1117/12.45892

1 July 1991 Miniaturized low-power parallel processor for space applications

William J. Jacobi, Preben D. Jensen, Nicholas J. Teneketges, Leo A. Wadsworth

Proceedings Volume 1495, Small-Satellite Technology and Applications; (1991) https://doi.org/10.1117/12.45892
Event: Orlando '91, 1991, Orlando, FL, United States

Abstract

A miniaturized, low-power parallel processor for space applications is under development by Space Computer Corporation for DARPA's Advanced Space Technology Program. The basic goal of this project is the reduction, by an order of magnitude or more, of on-board processor weight, size, and power consumption for space-based sensor systems. The approach described here for achieving this goal is to use low-power VLSI devices which maximize throughput per watt, together with three-dimensional hybrid wafer-scale integration and packaging technology. In its prototype version, a 12-node processor will have a peak throughput greater than 1.2 GFLOPS and occupy a volume less than 15 cubic inches.

Citation Download Citation

William J. Jacobi, Preben D. Jensen, Nicholas J. Teneketges, and Leo A. Wadsworth "Miniaturized low-power parallel processor for space applications", Proc. SPIE 1495, Small-Satellite Technology and Applications, (1 July 1991); https://doi.org/10.1117/12.45892

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