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8 November 2024 Design of timing control circuit for infrared detector based on JESD204B
Renkai Chen, Hua Wang, Yuqiang Wang, Dong Yu, Xinchuan You
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Proceedings Volume 13247, Infrared, Millimeter-Wave, and Terahertz Technologies XI; 1324709 (2024) https://doi.org/10.1117/12.3035981
Event: SPIE/COS Photonics Asia, 2024, Nantong, Jiangsu, China
Abstract
In this paper, a timing control circuit for infrared detectors is designed based on JESD204B high-speed serial interface technology, and a corresponding verification scheme is proposed. The timing control circuit of the infrared detector consists of a JESD204B high-speed data transmission module and a control clock generation module, used for data transmission and control timing generation in the infrared detector imaging circuit. The timing generation module can adjust the register status through SPI to meet the timing requirements of multiple detectors; The data transmission module outputs high-speed serial data through two JESD204B transmission interfaces for 8-channel LVDS digital data according to the protocol, reducing the data interface with the main control circuit. The high-speed data transmission function is verified using a timing control circuit as the transmitter and FPGA as the receiver. The FPGA received the data correctly and met a serial data transmission rate of 4.096Gbps; Verified the function of controlling timing generation, the timing control circuit is based on the main clock and can correctly generate control signals for various modules inside the circuit.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
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Renkai Chen, Hua Wang, Yuqiang Wang, Dong Yu, and Xinchuan You "Design of timing control circuit for infrared detector based on JESD204B", Proc. SPIE 13247, Infrared, Millimeter-Wave, and Terahertz Technologies XI, 1324709 (8 November 2024); https://doi.org/10.1117/12.3035981
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KEYWORDS
Infrared detectors
Clocks
Data transmission
Field programmable gate arrays
Design
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