Paper
1 June 1990 Methodology to reduce chronic defect mechanisms in semiconductor processing
Timothy W. Ecton, Kenneth G. Frazee
Author Affiliations +
Abstract
This paper docuitents a structur approach to defect elimination in seiiiccructor processing. Classical problem solving techniques were used to logically guide the defect rIuction effort. tfect infontation was gatherei using an automated wafer inspection systeaii ar defects were classifi&1 by production workers on a rete review station. This approach distiruishe actual causes from several probable causes. A process change has reduc the defect mechanism. This methodology was applied to ruce !IEFWN' perfluoroalkoxy (PFA) particles in a one micron semiccructor process. Electrical test structures identified a critical layer where yield loss was occurring. An audit procedure was establishi at this layer arx defects were c1assifi into broad cateories. Further breakout of defect t'pes by appearance was necessaxy to construct a meaningful Pareto chart ard identify the xist fr&ijiently occurring fatal defect. The critical process zone was segmented using autaat wafer inspection to isolate the step causing the defect. An IshiJcawa or cause-effect diagram was construct with input from process engineers to outline all possible causes of the defect. A nest probable branch was selected for investigation arxi pursued until it became clear that this branch was not related to the cause. At this point, new ideas were sought from a sister production facility. ring the visit a breakthrough irxicat& a different path ar ultiltiately lead to identifying the source of the defect. A process change was implemented. An evaluation of the change she1 a substantial decrease in defect evel. rther efforts to eliminate the defect srce are in rogres.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Timothy W. Ecton and Kenneth G. Frazee "Methodology to reduce chronic defect mechanisms in semiconductor processing", Proc. SPIE 1261, Integrated Circuit Metrology, Inspection, and Process Control IV, (1 June 1990); https://doi.org/10.1117/12.20064
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CITATIONS
Cited by 1 scholarly publication.
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KEYWORDS
Semiconducting wafers

Particles

Inspection

Integrated circuits

Process control

Wafer inspection

Metrology

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