Control of wafer backside defectivity is a challenge during the chip manufacturing process and has been extensively investigated throughout the past decade, especially on immersion lithography systems. As technology nodes continue to scale down and we approach the high NA EUV lithography era, backside contamination is becoming a critical problem. High NA EUV exposure systems have a smaller depth of focus compared to low NA EUV systems. The presence of backside wafer defects can easily lead to focus loss or on-product overlay errors leading to pattern failures. To anticipate the upcoming challenges, SCREEN has developed a sophisticated track-integrated backside cleaning (BSC) module on the DT-3000 system. This enables an advanced post-coating BSC solution directly before exposure. Together ASML, imec and SCREEN, investigated the potential of this unique BSC process to extend the lithographic performance of EUV material stacks, by correlating backside contamination with frontside patterning performance and the minimization of scanner focus spots. With this approach, we try to identify and characterize potential backside defect killers that could cause not only yield loss, but also physical deterioration of the scanner wafer table (WT) and its lifetime.
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