A low power digital decimation filter circuit ASIC design for Sigma-Delta ADC

Zhaoyu Wang; Bo Fan; Huimin Liu

doi:10.1117/12.2637056

15 June 2022 A low power digital decimation filter circuit ASIC design for Sigma-Delta ADC

Zhaoyu Wang, Bo Fan, Huimin Liu

Proceedings Volume 12285, International Conference on Advanced Algorithms and Neural Networks (AANN 2022); 1228506 (2022) https://doi.org/10.1117/12.2637056
Event: International Conference on Advanced Algorithms and Neural Networks (AANN 2022), 2022, Zhuhai, China

Abstract

As an important component of Sigma-Delta (Σ-Δ)ADCs, the performance of the digital filter has a direct and important impact on the accuracy. In this paper, a 17-bit precision Σ-Δ ADC digital filter is designed with a cascaded integrated combination (CIC) filter and a half-band filter cascade, and graded downsampling using a two-band CIC filter and a two-band half-band filter.By optimizing the order of the half-band filterand using CSD encoding to reduce hardware resource consumption and improve computing performance. The filter is simulated on FPGA, and the maximum operating speed of the filter is 43.19MHz, which meets the real-time input of the sample rate signal. The output SNR is 105.86dB, and the ENOB is 17.29bits. Finally, a full custom digital circuit layout design for the digital filter was implemented based on a 0.18μm CMOS technology with a layout area of 41878μm² and a total power of 378μW.

Citation Download Citation

Zhaoyu Wang, Bo Fan, and Huimin Liu "A low power digital decimation filter circuit ASIC design for Sigma-Delta ADC", Proc. SPIE 12285, International Conference on Advanced Algorithms and Neural Networks (AANN 2022), 1228506 (15 June 2022); https://doi.org/10.1117/12.2637056

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