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In advanced lithography, controlling overlay budget is critical, and how to control on production overlay(OPO) quality well as 100% measurement sampling in high volume manufacturing fab will be an impossible mission. Nevertheless, most of HVM fabs encounter with almost the same problem for low sampling lot, wafers, even less measurement points by reason of facility and Fab space issue and cost. No matter how critical overlay need, the advanced process correction (APC) maintaining the overlay performance under 10%~15% lot base sampling with 4 wafers may be the limitation in most of HVM fabs. Base on the 100% measurement conception and possibility, CXMT begin to study ASML cMetro (computation Metrology) possibility through measuring uDBO in Yield Star and combining with scanner leveling information, coming to catch overlay issue wafers and make sure overlay quality as 100% sampling measurement. To achieve this, conventionally, users try to study process possibility in leveling information between with overlay behaviors under the immersion critical layers. To identify the layer strategy and program successful, how to input and build-up cMetro modeling is reasonable and the monitor result is anticipated catching inline overly issue lots under cMetro prediction will be vitally important, no matter going through scanner leveling data method or combining with uDBO measurement as HDOM model. However, this approach will be time-consuming in the beginning due to not only several leveling condition and spilt are necessary, but also need to collect SSO (sampling scheme optimization) or sparse map and high dense map in uDBO measurement. Aiming to speed up the turnaround time, CXMT focus on layers with warpage experience and define the lots & wafers & map sampling to find the correlation. As a results, cMetro HDOM model monitor is possibility to hold up the issue overlay lots even under real inline measurement sampling for 10~15%.
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