Methodologies to handle large volumes of design and defect data for improved pre-silicon defect prediction

Parnashri Wankhede; Devansh Singh; Manish Kumar Sahu; Aruna Veluru; Monisa Ramesh Babu; Chenlong Miao; Shenghua Song; Shobhit Malik; Sriram Madhavan

doi:10.1117/12.2614185

26 May 2022 Methodologies to handle large volumes of design and defect data for improved pre-silicon defect prediction

Parnashri Wankhede, Devansh Singh, Manish Kumar Sahu, Aruna Veluru, Monisa Ramesh Babu, Chenlong Miao, Shenghua Song, Shobhit Malik, Sriram Madhavan

Author Affiliations +

Proceedings Volume 12052, DTCO and Computational Patterning; 1205210 (2022) https://doi.org/10.1117/12.2614185
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States

Abstract

The goal of this study is to discuss the findings of experiments we conducted to enhance defect capture rate in the advanced nodes design-for-manufacturing flow. As a metric of manufacturing excellence, wafer fabrication units track and report defect density on a regular basis. Fabrication with a reduced defect density can produce a higher chip yield. In recent years, systematic defects resulting from design and process have been predicted to be the leading cause of yield loss. This could result in a large rise in manufacturing costs and time. As a result, they are highly undesirable, and it is critical to accurately identify them for root analysis of weak patterns. Unlike random process defects, systematic patterning defects may show characteristic design features and our goal is to leverage these to create a machine learning model that can efficiently identify and categorize these defects before they get into production. An inherent problem that we face is class imbalance: high confidence defect data constitutes a few thousand samples for maturing nodes and nondefects of the order of millions. Additionally, millions of records in the train, test, and inference datasets, even with reduced feature sets, can lead to a host of big data issues like insufficient memory, large experiment times, and lack of integrated development. In this paper, we discuss methodologies to handle the large volume, imbalanced data which led to 47% improvement in the defect capture and 100% improvement in the noise to signal ratio.

Conference Presentation

Citation Download Citation

Parnashri Wankhede, Devansh Singh, Manish Kumar Sahu, Aruna Veluru, Monisa Ramesh Babu, Chenlong Miao, Shenghua Song, Shobhit Malik, and Sriram Madhavan "Methodologies to handle large volumes of design and defect data for improved pre-silicon defect prediction", Proc. SPIE 12052, DTCO and Computational Patterning, 1205210 (26 May 2022); https://doi.org/10.1117/12.2614185

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