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Curvilinear design layout is becoming increasingly prevalent in semiconductor manufacturing industry. One of the applications is Silicon Photonics. Silicon Photonics design layout requires the use of curvilinear shapes to minimize the loss of signal strength. Other applications include curvilinear Mask Proximity Correction (CL MPC), verification (CL MPCV), Mask Rule Checking (CL MRC), microelectromechanical system (MEMS), on-chip metasurface optics, etc. Curvilinear design layout poses new challenges to computational lithography tools that were developed mainly to handle Manhattan geometries. It has been found that the geometry-based error classification used in the Optical Proximity Correction (OPC) verification flow has its limitations to support curvilinear designs. In this paper, we present our innovative work of using Siemens EDA Calibre® OPCVerify Machine Learning (ML) Classify technology to classify error markers in the feature vector space instead of traditional pattern’s vertices and edges geometries. There are five steps in our OPCVerify ML Classify: 1. use primary checks to output error markers, 2. design features and create feature vector kernels, 3. collect feature vectors at error marker locations, 4. prepare patterns with pre-knowledge of desired classify guidance and train ML model, and 5. apply ML classify model to classify error markers on full layout in the feature vector space. In our experiments, ML Classify is successful in classifying OPC verification error markers in curvilinear designs. A drawn silicon photonics layout with 837,072 raw error locations has demonstrated our ML Classify tool’s capability to reduce the unique class count from 221,085 based on conventional geometry-based classify approach down to 51. We also developed further sub-classify feature which provides options to further sub-classify results by edge types, convex, concave, or straight line, and by polygon’s internal width and external space to neighboring polygons. The 51 unique class count becomes 2493 after the further sub-classify process. This methodology is not only good for silicon photonics application, but also good for other curvilinear photomask applications, like CL MPCV, MEMS, on-chip metasurface optics, and in general even Manhattan designs.
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