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With continued innovation of semiconductor processes, overlay control has become the most critical and challenging part. Advanced technology nodes require even tighter lithography overlay control, and therefore, high-order process corrections for inter-field (HOPC) and for intra-field (iHOPC) are adopted as a common solution to meet on-product overlay (OPO) specifications. High order corrections often require more measurement shots and more targets in field, which makes optical overlay metrology on scribe line targets the workhorse of overlay control due to its high throughput and low cost-of-ownership. This leads to the additional challenge that the measurement location also affects the accuracy of generated overlay corrections. For example, it is well known that there may be a spatially dependent offset between overlay on targets and the device. This is commonly called a non-zero offset (NZO) [1], which is a comparison between device overlay measured with the CD SEM after etching (AEI) and optical overlay measured on targets after litho (ADI). In addition, the position of targets could impact the validity of corrections modeled using these targets. The targets could be unevenly distributed in field, some targets huddle at an area, while not a single target appears at others. Hence, this kind of target layout has risks generating problematic field corrections at areas without enough targets. In this paper, we propose a hybrid method utilizing CDSEM overlay to fill in the position where optical overlay targets are deficient. With iHOPC model terms generated by optical overlay targets only, CDSEM metrology results from real devices reveal significantly larger overlay in areas with no targets. By means of this method, the mis-correction at locations where optical overlay targets are deficient is significantly restored, and consequently the OPO mean+3sigma is suppressed to <4nm. Furthermore, an inline control solution is proposed and implemented with the latest generation 5D Analyzer.
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