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6 November 2019 IPbus bus functional model in universal VHDL verification methodology
Michał Kruszewski
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Proceedings Volume 11176, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019; 1117644 (2019) https://doi.org/10.1117/12.2536696
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019, 2019, Wilga, Poland
Abstract
Simulation-based functional verification is an important part of a Field-Programmable Gate Array (FPGA) design flow. It is desirable of test bench to be written quickly, with high abstraction and in understandable way. The paper describes IPbus Bus Functional Model (BFM) that has been implemented in the Universal VHDL Verification Methodology (UVVM) test bench infrastructure. It also presents a simple example how the module should be used.
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Michał Kruszewski "IPbus bus functional model in universal VHDL verification methodology", Proc. SPIE 11176, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019, 1117644 (6 November 2019); https://doi.org/10.1117/12.2536696
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KEYWORDS
Field programmable gate arrays
Reliability
Application specific integrated circuits
Computer programming
Integrated circuits
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